1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming a polysilicon gate layer which inhibits the penetration of ions into the underlying gate oxide in the fabrication of integrated circuits.
2. Description of the Prior Art
In the manufacture of integrated circuits, it is a conventional process to use a polysilicon gate. The polysilicon is grown at a temperature of about 620.degree. C. until the desired thickness is reached. Since the temperature is held constant throughout the growth of the polysilicon, the polysilicon grains will be column-like. FIGS. 1 and 2 illustrate a partially completed integrated circuit of the prior art in which a layer of silicon oxide 12 has been grown on a semiconductor substrate. Polysilicon layer 14 has been grown at a constant temperature of 620.degree. C., as described above.
In FIG. 1, when B+ or BF.sub.2 + ions are implanted 16 into the polysilicon layer 14, the B+ ions easily diffuse through the column-like grain boundaries of the polysilicon into the gate oxide layer 12. Similarly, in FIG. 2, when the polysilicon layer 14 is capped with a tungsten silicide film 18, F- ions easily diffuse through the column-like grain boundaries of the polysilicon into the gate oxide layer 12. As a consequence of this diffusion, the gate oxide effective thickness will be increased. Also, especially in the case illustrated by FIG. 2, electron traps are created within the gate oxide layer. The B+ penetration will cause threshold voltage shift causing device and circuit failure.
The present invention uses a multilayer polysilicon gate with mismatched grain boundaries to confine the ions within the polysilicon and inhibit the penetration of the ions into the underlying gate oxide.
A multilayer concept has been used in a number of patents, although the layers are composed of different materials and/or they are used for different purposes than that of the present invention. U.S. Pat. No. 4,354,309 to Gardiner et al describes a process in which multiple polysilicon layers having differing dopant concentrations are used to limit grain size. U.S. Pat. No. 4,329,706 to Crowder et al details an improved interconnection for integrated circuits using layers of polysilicon and metal silicide. U.S. Pat. No. 5,350,698 to Huang et al describes a self-aligned gate formed of layers of polysilicon and native oxide.
U.S. Pat. No. 4,663,825 to Maeda describes a method for mechanically breaking down a native oxide film formed at the interface of a conducting layer and a wiring layer.
U.S. Pat. No. 4,697,333 to Nakahara teaches a method of preventing penetration of ions by converting some or all of a polysilicon layer to amorphous silicon before ion implantation.